The CPU is the core of the VO-EM machine. It handles all non-graphical processing. It is closely based on the theoretical DLX CPU, but currently does not implement the floating point unit. As in, anything that compiles or assembles bytecode for the DLX CPU should theoretically run on the VO-EM CPU. Unless it uses floating point math.
Clock speed: 72,000 instructions per second
Instruction length: 4 bytes
The CPU's clock cycle has two phases - Fetch and Execute.
In the Fetch cycle, the CPU first checks for, and handles, any interrupts or exceptions that have occurred since the last cycle.
If the [Opcodes#wait|wait] instruction has been used and no exceptions have occurred, the CPU will stop here and continue waiting for an interrupt or exception.
Otherwise, the CPU will read the data located at the address currently indicated by PC into IR, then increment PC by 4.
The CPU decodes the instruction in IR, and then executes it.
There are 32 general purpose registers in the VO-EM CPU, named r0 to r31. r0 always contains zero, regardless of what is written to it. Each register is 32 bits long.
In addition to the general purpose registers, there are some special registers that perform specific functions. Some can be accessed directly.
PSW, XBR and XAR can be read and written using [[[Opcodes#movs21|movs2i]]] and [[[Opcodes#movi2s|movi2s]]] respectively.
- Program Counter
- This register contains the address of the next instruction to be loaded. It can be changed using jump commands. It cannot be read directly.
- Instruction Register
- Contains the instruction to be executed. Cannot be read or written to.
- Processor Status Word
- Controls interrupt and exception handling.
- Exception Base Register
- This is the address of your interrupt and exception handling jump table.
- Exception Address Register
- When an exception occurs, the address of the instruction that caused the exception is stored here.
- Main article: Opcodes
The VO-EM CPU uses entirely 4-byte instructions. See the opcode reference for detailed information regarding them.
When an instruction is loaded, it is loaded with a lw operation, meaning that its address must be aligned to a multiple of 4, or the read will fail.